1. Field of the Invention
This invention relates to electrodeposition of metals and more particularly to electrodeposition of metals into microscopic recesses on the surface of a substrate and formation of uniform layers of electrodeposited metal on a substrate.
2. Brief Description of the Prior Art
The manufacture of semiconductor devices, especially very large scale integrated (VLSI) chips is driven by technical and economic considerations toward the production of devices comprising greater numbers of transistors and associated circuits on a single semiconductor chip or wafer. The most complex chips manufactured today have a few million transistors on a semiconductor chip no larger than several millimeters on a side. The electrical interconnections between the transistors in such chips are provided by fine wires of a conductive metal extending in channels formed horizontally and vertically in the body of the chip. Conventionally, these electrical connections have been made of aluminum, which can be deposited through vapor phase deposition techniques such as physical vapor deposition (PVD) and chemical vapor deposition (CVD). However, as the dimensions of the transistors have decreased into the submicron region, the cross sections of the connections have also decreased and the resistance of the connections has increased. In order to reduce the resistance of the connections in VLSI circuits containing devices of submicron dimensions, the use of copper as a connecting material has come to be favored.
Furthermore, as the dimensions of the interconnections between the devices have decreased, the use of conductors of high aspect ratio has become desirable. When VLSI devices are prepared by the damascene process, which requires that the conducting metal be deposited into trenches formed in a layer of insulating material, it has been found difficult to achieve void-free metal deposits in trenches having high aspect ratios by PVD or CVD.
Attempts have been made to deposit copper conductors into trenches on damascene-prepared surfaces by electroplating. However, it has proved difficult to prepare void-free, and inclusion-free deposits in trenches of high aspect ratio. Furthermore, electroplating of copper into trenches of a damascene-prepared surface has required depositing a relatively thick layer of copper over the entire surface of the wafer. The excess copper must then be removed by chemical-mechanical polishing (CMP), which is a time-consuming process that also generates substantial amounts of waste slurries that require careful and expensive disposal procedures.
Electroplating has also been used to deposit a thin layer of copper on the surface of a large semiconductor wafer preparatory to forming electrical interconnections by the customary masking and etching procedures. However, because of the tendency of electroplating procedures to deposit excess metal at the edges of the wafer, it has proved difficult to prepare perfectly uniform layers of copper. Auxiliary electrodes have been used to surround the edges of the wafer in order to provide a uniform electric field, as disclosed, for example in U.S. Pat. No. 5,135,636, to Yee et al. However, such procedures require additional equipment and are evidently wasteful of copper metal.
Accordingly, a need has continued to exist for a method of depositing metallic conductors, especially copper, in damascene trenches and for depositing a thin uniform layer of a metal such as copper over the entire surface of a semiconductor wafer with minimal need for subsequent planarization.